Citation:

Syamsuddin Millang, Siti Nuraeni, 2023. LDPC Decoders for the Design and Implementation of High Performance and Low Cost Techniques, ESP Journal of Engineering & Technology Advancements  3(3): 23-28.

Abstract:

Scaling of technology and increased integration density can cause parameter and noise changes, which can increase error rates at different stages of computing. Soft failures and single-event upsets are a persistent issue in memory applications. This work is primarily concerned with the design of an effective Multi Detector/Decoder (MLDD) for fault detection and fault correction in memory applications. One-step majority logic decoding is used to effectively discover and rectify errors in Euclidean Geometry Low Density Parity Check Codes (EG-LDPC). While majority decodable codes have the potential to fix a huge number of mistakes, their lengthy decoding times mean that errors are more likely to be missed, and the ML Decoding technique might waste time by identifying faults in both error- and error-free code words. The suggested fault-detection approach can identify the error in nearly three decoding cycles. Memory access time can be decreased when the data read is mistake free. For high code word sizes, the approach maintains small area overhead and low power consumption.

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Keywords:

LDPC Decoders, Multi Detector, ML Decoding, Memory.