Citation:

Mohandass, 2025. "Design of Low-Power VLSI Circuits Using Approximate Computing for IOT.", ESP Journal of Engineering & Technology Advancements  5(2): 249-258.

Abstract:

The fast expanding Internet of Things (IoT) has produced an exponential increase in the number of linked devices, all of which demand great performance within rigorous power, area, and cost constraints. Conventional VLSI design techniques—which give accuracy and predictable performance top priority—are increasingly unsustainable for IoT edge nodes with constrained resources. Usually having limited battery life, these devices are situated in environments where low latency, real-time data processing, and long operational lifetime are vitally essential. Approximate computing (AC) has evolved into a revolutionary design paradigm within this framework allowing purposeful, controlled errors in computation to reach significant benefits in energy economy, area reduction, and processing speed.Many IoT devices—including environmental sensing, health monitoring, picture identification, and audio analysis—have natural error resilience that approximates computing takes advantage of. These systems can resist small fluctuations in computing results without compromising their general performance or usability. This abstract considers how low-power VLSI circuit design might include approximative computing techniques with an eye on IoT system performance. From logic gates to arithmetic units and architectural frameworks, it looks at how to employ approximation at multiple levels to achieve energy-aware VLSI design.Applied at the circuit level, techniques including voltage scaling, logic reduction, and signal pruning build approximative arithmetic units comprising adders, multipliers, and accumulators, so constituting the computational backbone of most IoT processors. By eliminating redundant or non-essential logic lines, these designs drastically reduce power consumption and silicon area, therefore affecting output quality very little. Moreover, architecture-level approximations such reconfigurable functional units and low-precision datapaths allow adjustable trade-offs between energy economy and accuracy that may be dynamically modified depending on real-time performance needs.Moreover included in the study is the importance of error tolerance analysis within the scope of Internet of Things implementations. Knowing application-specific thresholds for acceptable error allows one to advise the degree and sort of approximation to be employed. A minor fluctuation in temperature sensing would be reasonable for a smart thermostat, for example; but, this would not be so in a medical device. Moreover under discussion as a required enabler for developing and verifying approximative VLSI circuits is the development of approximative-aware EDA tools and simulation environments. These tools ensure dependability and resilience even in the midst of intentional computational imprecision, hence supporting the evaluation of power-accuracy trade-offs.Notwithstanding its potential, acceptance of approximative computing in mainstream VLSI design is still limited due of problems including lack of standardising, limited design automation support, and possible security weaknesses. Still, hybrid computing systems that cleverly combine accurate and approximative computation will most likely guide IoT-oriented hardware design.At last, approximation computing represents a paradigm change in VLSI design that precisely satisfies IoT low-power, high-efficiency requirements. By accepting imperfection when suitable, designers can unlock new levels of energy efficiency and performance scalability, therefore offering an interesting route for next low-power embedded system research and development.

References:

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[12] May, D.; Stechele, W. 2016 marks. Sequential circuits for approximate computation: voltage over-scaling. 2016 Design and Technology of Integrated Systems in Nanoscale Era (DTIS) International Conference IEEE.Springer Link

[13] Liu, W., Xu, J., Wang, D.; Wang, C.; Montuschi, P.; Lombardi, F. 2018: Approximate Logarithmic Multipliers for Low Power Error-Tolerant Applications: Design and Evaluation I: Regular Papers, IEEE Transactions on Circuits and Systems I: 65(9), 2856–2868 10.1109/TCSI.2018.2809649SpringerLink https://doi.org/10.1109/TCSI.2018.2809641

[14] Chouhary, P.; Bhargava, L.; Fujita, M.; Singh, V.; Suhag, A. K. (2022). Arithmetic Circuit Approximation for Internet of Things Data Processing. Computers and industrial engineering, 174, 108792. https://doi.org/10.1016/j.cie.2022.108492SpringerLink

[15] Gupta, V., Mohapatra, D.; Park, S. P.; Raghunathan, A.; Roy, K. 2013: IMPACT: Perfect Adders for Low-Power Approximate Computing. In Low Power Electronics and Design (ISLPED) (pp.409–414) 17th IEEE/ACM International Symposium 10.1145/2485288. 24853 https://doi.org/

[16] Mahdiani, H. R.; Ahmadi, A; Fakhraie, S. M.; Lucas, C. 2010 stands for Precision Computational Blocks Inspired by Nature for Effective VLSI Soft-Computing Application Implementation 57(4), 850–862 IEEE Transactions on Circuits and Systems I: Regular Papers. 10.1109/TCSI.2009.2027626SpringerLink @ doi.org/10.1109

[17] Zhu, N.; Goh, W. L.; Wang, G; & Yeo, K. S. 2010 is the year Improved Low-Power High-Speed Adder for Application with Error-Tolerance. Proceedings of the 2010 IEEE International Symposium on Integrated Circuits (pp. 69–72) SpringerLink

[18] Kahng, A. B. and Kang, S. In 2012. Accuracy-adjustable Adder for approximative arithmetic designs. In the 49th ACM/EDAC/IEEE Design Automation Conference (DAC), pp. 820–825 http://doi.org/10.1145/2228360.2228509SpringerLink

[19] Singh, V.; Bhargava, L.; Choudhary, P. (2023). Comparative Study and Evaluation of Approximate Adder Circuits. PCCDS 2022: Proceedings of the International Conference on Paradigms of Computing, Communication and Data Sciences: PCCDS 2022 (pp. 519–533). Springer: Springer Link

[20] May, D.; Stechele, W. 2016 marks. Sequential circuits for approximate computation: voltage over-scaling. 2016 Design and Technology of Integrated Systems in Nanoscale Era (DTIS) International Conference IEEE.Springer Link

[21] Chouhary, P.; Bhargava, L.; Fujita, M.; Singh, V.; Suhag, A. K. (2022). Arithmetic Circuit Approximation for Internet of Things Data Processing. Computers and industrial engineering, 174, 108792. 10.1016/j.cie.2022.108792 https://doi.org/10.1016/j.cie.2022.108592

[22] Gupta, V.; Mohapatra, D.; Park, S. P.; Raghunathan, A.; & Roy, K. 2013: IMPACT: Perfect Adders for Low-Power Approximate Computing. In Low Power Electronics and Design (ISLPED) (pp.409–414) 17th IEEE/ACM International Symposium 10.1145/2485288. 24853 https://doi.org/

[23] Mahdiani, H. R.; Ahmadi, A; Fakhraie, S. M.; Lucas, C. 2010 stands for Precision Computational Blocks Inspired by Nature for Effective VLSI Soft-Computing Application Implementation Regular Papers, 57(4), 850–862 IEEE Transactions on Circuits and Systems I. https://doi.org/10.1109/TCSI.2009.20276

[24] Zhu, N.; Goh, W. L.; Wang, G.; & Yeo, K. S. 2010 is the year Improved Low-Power High-Speed Adder for Application with Error-Tolerance. In 2010 IEEE International Symposium on Integrated Circuits, p. 69–72.

[25] Kang, S. and Kahng, A. B. In 2012. Accuracy-adjustable Adder for approximative arithmetic designs. In the 49th ACM/EDAC/IEEE Design Automation Conference (DAC), pp. 820–825 http://doi.org/10.1145/2228360.2228509

Keywords:

Low-Power VLSI, Approximate Computation, Iot, Energy-Efficient Design, Approximate Arithmetic Units, Error-Tolerant Circuits, Edge Computing, Power Optimisation, Circuit-Level Approximation, Architecture-Level Approximaton.